SH7729R Datasheet, PDF (12/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Section
9.3.1 Transition to
Sleep Mode
Page
233
9.5.1 Transition to 237
Module Standby
Function
10.2.1 CPG Block
250
Diagram
Figure 10.1 Block
Diagram of Clock Pulse
Generator
Description
Description added
In sleep mode, the STATUS1 pin is set high and the STATUS0
pin low.
DMAC transfers should not be performed in the sleep mode
under conditions other than when the clock ratio of I0 (on-chip
clock) to B0 (bus clock) is 1:1.
Note *3 added to bit table
Note: 3. Before putting the RTC into module standby status, first
access one or more of the RTC, SCI, and TMU
registers. The RTC may then be put into module standby
status.
Figure amended
Clock pulse generator
CAP1
CKIO
Cycle = Bcyc
CAP2
XTAL
EXTAL
Crystal
oscillator
PLL circuit 1
(× 1, 2, 3, 4,
6)
PLL circuit 2
(× 1, 4)
Divider 1
×1
× 1/2
× 1/3
× 1/4
× 1/6
Divider 2
×1
× 1/2
× 1/3
× 1/4
× 1/6
Internal
clock (Iφ)
Cycle = Icyc
Peripheral
clock (Pφ)
Cycle = Pcyc
Rev. 5.0, 09/03, page xii of xlvi