SH7729R Datasheet, PDF (252/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bits 7 and 6—CPU Cycle/DMAC Cycle Select B (CDB1, CDB0): Select a CPU cycle or
DMAC cycle as the bus cycle of the channel B break condition.
Bit 7: CDB1 Bit 6: CDB0
0
0
*
1
1
0
Note: * Don’t care.
Description
Condition comparison is not performed
Break condition is CPU cycle
Break condition is DMAC cycle
(Initial value)
Bits 5 and 4—Instruction Fetch/Data Access Select B (IDB1, IDB0): Select an instruction fetch
cycle or data access cycle as the bus cycle of the channel B break condition.
Bit 5: IDB1
0
1
Bit 4: IDB0
0
1
0
1
Description
Condition comparison is not performed
(Initial value)
Break condition is instruction fetch cycle
Break condition is data access cycle
Break condition is instruction fetch cycle or data access cycle
Bits 3 and 2—Read/Write Select B (RWB1, RWB0): Select a read cycle or write cycle as the
bus cycle of the channel B break condition.
Bit 3: RWB1
0
1
Bit 2: RWB0
0
1
0
1
Description
Condition comparison is not performed
Break condition is read cycle
Break condition is write cycle
Break condition is read cycle or write cycle
(Initial value)
Bits 1 and 0—Operand Size Select B (SZB1, SZB0): Select the operand size of the bus cycle for
the channel B break condition.
Bit 1: SZB1
0
1
Bit 0: SZB0
0
1
0
1
Description
Break condition does not include operand size (Initial value)
Break condition is byte access
Break condition is word access
Break condition is longword access
Rev. 5.0, 09/03, page 206 of 806