SH7729R Datasheet, PDF (67/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

31
R0_BANK0^{*1 *2}
R1_BANK0^*2
R2_BANK0^*2
R3_BANK0^*2
R4_BANK0^*2
R5_BANK0^*2
R6_BANK0^*2
R7_BANK0^*2
R8
R9
R10
R11
R12
R13
R14
R15
0 31
R0_BANK1^{*1 *3}
R1_BANK1^*3
R2_BANK1^*3
R3_BANK1^*3
R4_BANK1^*3
R5_BANK1^*3
R6_BANK1^*3
R7_BANK1^*3
R8
R9
R10
R11
R12
R13
R14
R15
0 31
0
R0_BANK0^{*1 *4}
R1_BANK0^*4
R2_BANK0^*4
R3_BANK0^*4
R4_BANK0^*4
R5_BANK0^*4
R6_BANK0^*4
R7_BANK0^*4
R8
R9
R10
R11
R12
R13
R14
R15
SR
SR
SR
SSR
SSR
GBR
MACH
MACL
PR
GBR
MACH
MACL
PR
VBR
GBR
MACH
MACL
PR
VBR
PC
PC
PC
SPC
SPC
R0_BANK0^{*1 *4}
R1_BANK0^*4
R2_BANK0^*4
R3_BANK0^*4
R4_BANK0^*4
R5_BANK0^*4
R6_BANK0^*4
R7_BANK0^*4
R0_BANK1^{*1 *3}
R1_BANK1^*3
R2_BANK1^*3
R3_BANK1^*3
R4_BANK1^*3
R5_BANK1^*3
R6_BANK1^*3
R7_BANK1^*3
(a) User mode register
configuration
(b) Privileged mode register (c) Privileged mode register
configuration (RB = 1)
configuration (RB = 0)
Notes: 1. The R0 register is used as an index register in indexed register indirect addressing mode
and indexed GBR indirect addressing mode.
2. Bank register
3. Bank register
Accessed as a general register when the RB bit is set to 1 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is cleared to 0.
4. Bank register
Accessed as a general register when the RB bit is cleared to 0 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is set to 1.
Figure 2.1 Register Configuration in Each Processing Mode (1)
Rev. 5.0, 09/03, page 21 of 806