SH7729R Datasheet, PDF (834/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Control Register Module^*1 Bus^*2 Address^*4 Size (Bits) Access Size (Bits)^*3
SCSCR1
IrDA
P H'04000144
8
8
SCFTDR1
IrDA
P H'04000146
8
8
SCSSR1
IrDA
P H'04000148
16
16
SCFRDR1
IrDA
P H'0400014A
8
8
SCFCR1
IrDA
P H'0400014C
8
8
SCFDR1
IrDA
P H'0400014E
16
16
SCSMR2
SCIF
P H'04000150
8
8
SCBRR2
SCIF
P H'04000152
8
8
SCSCR2
SCIF
P H'04000154
8
8
SCFTDR2
SCIF
P H'04000156
8
8
SCSSR2
SCIF
P H'04000158
16
16
SCFRDR2
SCIF
P H'0400015A
8
8
SCFCR2
SCIF
P H'0400015C
8
8
SCFDR2
SCIF
P H'0400015E
16
16
SDIR
UDI
I H'04000200
16
16
SDSR
UDI
I H'04000204
16
16
SDDR/SDDRH
UDI
I H'04000208
16/32
16/32
SDDRL
UDI
I H'0400020A
16
16
SDAR
UDI
I H'0400020C
16
16
SDARE
UDI
I H'04000210
16
16
Notes: 1. Modules:
CCN: Cache controller
UBC: User break controller
CPG: Clock pulse generator BSC: Bus state controller
RTC: Realtime clock
INTC: Interrupt controller
TMU: Timer unit
SCI: Serial communication interface
2. Internal buses:
L: CPU, CCN, cache, TLB, and DSP connected
I: BSC, cache, DMAC, INTC, CPG, and UDI connected
P: BSC and peripheral modules (RTC, TMU, SCI, SCIF, IrDA, A/D, D/A, DMAC, ports,
CMT) connected
3. The access size shown is for control register access (read/write). An incorrect result
will be obtained if a different size from that shown is used for access.
4. To exclude area 1 control registers from address translation by the MMU, set the first 3
bits of the logical address to 101, to locate the registers in the P2 space.
5. With 16-bit access, it is not possible to read data in two registers simultaneously.
6. With 32-bit access, it is possible to read data in the register at [accessed address + 2]
simultaneously.
Rev. 5.0, 09/03, page 788 of 806