SH7729R Datasheet, PDF (366/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

When the WAITSEL bit in the WCR1 register is set to 1, the WAIT signal is sampled at the
falling edge of the clock. If the setup time and hold times with respect to the falling edge of the
clock are not satisfied, the value sampled at the next falling edge is used.
However, the WAIT signal is ignored in the following three cases:
• A write to external address space in dual address mode with 16-byte DMA transfer
• Transfer from an external device with DACK to external address space in single address mode
with 16-byte DMA transfer
• Cache write-back access
Wait states inserted
by WAIT signal
T₁
Tw
Tw
Tw
T₂
CKIO
A25 to A0
CSn
RD/WR
Read
RD
D31 to D0
Write
WEn
D31 to D0
WAIT
BS
Figure 11.11 Basic Interface Wait State Timing (Wait State Insertion by WAIT Signal
WAITSEL = 1)
Rev. 5.0, 09/03, page 320 of 806