SH7729R Datasheet, PDF (473/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

12.5 Examples of Use
12.5.1 Example of DMA Transfer between On-Chip IrDA and External Memory
In this example, receive data of the on-chip IrDA is transferred to external memory using DMAC
channel 3. Table 12.8 shows the transfer conditions and register settings. In addition, it is
recommended that the trigger for the number of receive FIFO data bytes in IrDA be set to 1
(RTRG1 = RTRG0 = 0 in SCFCR).
Table 12.8 Transfer Conditions and Register Settings for Transfer between On-Chip SCI
and External Memory
Transfer Conditions
Transfer source: RDR1 of on-chip IrDA
Transfer destination: External memory
Number of transfers: 64
Transfer source address: Fixed
Transfer destination address: Incremented
Transfer request source: IrDA (RXI1)
Bus mode: Cycle-steal
Transfer unit: Byte
Interrupt request generated at end of transfer
Channel priority order: 0 > 2 > 3 > 1
Register
SAR3
DAR3
DMATCR3
CHCR3
Setting
H'0400014A
H'00400000
H'00000040
H'00004B05
DMAOR
H'0101
Rev. 5.0, 09/03, page 427 of 806