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SH7729R Datasheet, PDF (704/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series | |||
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21.1.2 Block Diagram
Figure 21.1 shows a block diagram of the A/D converter.
Peripheral data bus
Internal
data bus
AVCC
AVSS
10-bit
D/A
AN0
AN1
+
AN2
AN3
Analog
AN4
multi-
AN5
plexer
â
Comparator
Control circuit
AN6
Sample-and-
AN7
hold circuit
ADTRG
A/D converter
Legend
ADCR: A/D control register
ADCSR: A/D control/status register
ADDRA: A/D data register A
ADDRB: A/D data register B
ADDRC: A/D data register C
ADDRD: A/D data register D
Figure 21.1 Block Diagram of A/D Converter
Rev. 5.0, 09/03, page 658 of 806
Ï/8
Ï/16
ADI
interrupt
signal
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