SH7729R Datasheet, PDF (53/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

1.2 Block Diagram
XYCNT
SH3
CPU
XYMEM
MMU
TLB
CCN
CACHE
BRIDGE
DSP
UBC
AUD
SCI
TMU
RTC
UDI
INTC
CPG/WDT
BSC
DMAC
CMT
IrDA
SCIF
ADC
DAC
External bus
interface
I/O port
Legend:
ADC:
A/D converter
AUD:
Advanced user debugger
BSC:
Bus state controller
CACHE: Cache memory
CCN:
Cache memory controller
CMT:
Compare match timer
CPG/WDT: Clock pulse generator/watchdog timer
CPU:
Central processing unit
DAC:
D/A converter
DMAC: Direct memory access controller
DSP:
Digital signal processor
UDI:
User debugging interface
INTC:
Interrupt controller
IrDA: Serial communicatiion interface (with IRDA)
MMU: Memory management unit
RTC: Realtime clock
SCI: Serial communication interface (with smart card interface)
SCIF: Serial communication interface (with FIFO)
TLB: Translation look-aside buffer
TMU: Timer unit
UBC: User break controller
XYCNT: X/Y memory controller
XYMEM: X/Y memory
Figure 1.1 Block Diagram
Rev. 5.0, 09/03, page 7 of 806