SH7729R Datasheet, PDF (287/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Standby to Power-On Reset
Oscillation stops Reset
CKIO, CKIO2^*7
RESETP^*1
STATUS
Normal^*5
Standby^*4 *2
Reset^*3
Normal^*5
0 to 10 Bcyc^*6
0 to 30 Bcyc^*6
Notes: 1. When standby mode is cleared with a power-on reset, the WDT does not count.
Keep RESETP low during the PLL’s oscillation settling time.
2. Undefined
3. Reset: HH (STATUS1 high, STATUS0 high)
4. Standby: LH (STATUS1 low, STATUS0 high)
5. Normal: LL (STATUS1 low, STATUS0 low)
6. Bcyc: Bus clock cycle
7. CKIO2 output can only be used in clock modes 0, 1, and 2.
Figure 9.5 Standby to Power-On Reset STATUS Output
Rev. 5.0, 09/03, page 241 of 806