SH7729R Datasheet, PDF (48/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 1.1 SH7729R Features
Item
CPU
DSP
Features
• Original Renesas Technology SuperH architecture
• Compatible with SH-1, SH-2, and SH-3 series at object code level
• 32-bit internal data bus
• General-registers
 Sixteen 32-bit general registers (eight 32-bit shadow registers)
 Eight 32-bit control registers
 Four 32-bit system registers
• RISC-type instruction set
 Instruction length: 16-bit fixed length for improved code efficiency
 Load/store architecture
 Delayed branch instructions
 Instruction set based on C language
• Instruction execution time: one instruction/cycle for basic instructions
• Logical address space: 4 Gbytes
• Space identifier ASID: 8 bits, 256 logical address spaces
• Five-stage pipeline
• Mixture of 16-bit and 32-bit instructions
• Multiplier, ALU, barrel shifter, and DSP register
• 16-bit × 16-bit → 32-bit one cycle multiplier
• Large DSP data registers
 Six 32-bit data registers
 Two 40-bit data registers
• Extended Harvard Architecture for DSP data bus
 Two data buses
 One instruction bus
• Max. four parallel operations: ALU, multiply, and two load or store
• Two addressing units to generate addresses for two memory access
• DSP data addressing modes: increment, indexing (with or without modulo
addressing)
• Zero-overhead repeat loop control
• Conditional execution instructions
• User DSP mode and privileged DSP mode
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