SH7729R Datasheet, PDF (30/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

20.5.2 Port D Data Register (PDDR) .............................................................................. 638
20.6 Port E................................................................................................................................. 639
20.6.1 Register Description ............................................................................................. 639
20.6.2 Port E Data Register (PEDR) ............................................................................... 640
20.7 Port F................................................................................................................................. 641
20.7.1 Register Description ............................................................................................. 641
20.7.2 Port F Data Register (PFDR)................................................................................ 642
20.8 Port G ................................................................................................................................ 643
20.8.1 Register Description ............................................................................................. 643
20.8.2 Port G Data Register (PGDR) .............................................................................. 644
20.9 Port H ................................................................................................................................ 645
20.9.1 Register Description ............................................................................................. 645
20.9.2 Port H Data Register (PHDR) .............................................................................. 646
20.10 Port J.................................................................................................................................. 647
20.10.1 Register Description ............................................................................................. 647
20.10.2 Port J Data Register (PJDR)................................................................................. 648
20.11 Port K ................................................................................................................................ 649
20.11.1 Register Description ............................................................................................. 649
20.11.2 Port K Data Register (PKDR) .............................................................................. 650
20.12 Port L................................................................................................................................. 651
20.12.1 Register Description ............................................................................................. 651
20.12.2 Port L Data Register (PLDR) ............................................................................... 652
20.13 SC Port .............................................................................................................................. 653
20.13.1 Register Description ............................................................................................. 653
20.13.2 SC Port Data Register (SCPDR) .......................................................................... 654
Section 21 A/D Converter ................................................................................................. 657
21.1 Overview ........................................................................................................................... 657
21.1.1 Features ................................................................................................................ 657
21.1.2 Block Diagram ..................................................................................................... 658
21.1.3 Input Pins.............................................................................................................. 659
21.1.4 Register Configuration ......................................................................................... 660
21.2 Register Descriptions......................................................................................................... 661
21.2.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 661
21.2.2 A/D Control/Status Register (ADCSR) ................................................................ 662
21.2.3 A/D Control Register (ADCR)............................................................................. 664
21.3 Bus Master Interface.......................................................................................................... 665
21.4 Operation........................................................................................................................... 666
21.4.1 Single Mode (MULTI = 0)................................................................................... 666
21.4.2 Multi Mode (MULTI = 1, SCN = 0) .................................................................... 668
21.4.3 Scan Mode (MULTI = 1, SCN = 1) ..................................................................... 670
21.4.4 Input Sampling and A/D Conversion Time .......................................................... 672
21.4.5 External Trigger Input Timing ............................................................................. 673
Rev. 5.0, 09/03, page xxx of xlvi