SH7729R Datasheet, PDF (39/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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Power-on Oscillation Settling Time ..................................................................... 709
Oscillation Settling Time on Return from Standby (Return by Reset) ................. 709
Oscillation Settling Time on Return from Standby (Return by NMI) .................. 710
Oscillation Settling Time on Return from Standby (Return by IRQ4 to IRQ0,
PINT0/1 and IRL3 to IRL0)................................................................................. 710
PLL Synchronization Settling Time during Standby Recovery (Reset or NMI) .. 711
PLL Synchronization Settling Time during Standby Recovery (IRQ/IRL or
PINT0/PINT1 Interrupt)....................................................................................... 711
PLL Synchronization Settling Time in Case of IRQ/IRL Interrupt ...................... 712
Reset Input Timing............................................................................................... 714
Interrupt Signal Input Timing............................................................................... 714
IRQOUT Timing .................................................................................................. 714
Bus Release Timing.............................................................................................. 715
Pin Drive Timing at Standby................................................................................ 715
Basic Bus Cycle (No Wait) .................................................................................. 718
Basic Bus Cycle (One Wait)................................................................................. 719
Basic Bus Cycle (External Wait, WAITSEL = 1) ................................................ 720
Burst ROM Bus Cycle (No Wait) ........................................................................ 721
Burst ROM Bus Cycle (Two Waits) .................................................................... 722
Burst ROM Bus Cycle (External Wait, WAITSEL = 1) ...................................... 723
Synchronous DRAM Read Bus Cycle (RCD = 0, CAS Latency = 1, TPC = 0) .. 724
Synchronous DRAM Read Bus Cycle (RCD = 2, CAS Latency = 2, TPC = 1) .. 725
Synchronous DRAM Read Bus Cycle (Burst Read (Single Read × 4),
RCD = 0, CAS Latency = 1, TPC = 1) ................................................................. 726
Synchronous DRAM Read Bus Cycle (Burst Read (Single Read × 4), RCD = 1,
CAS Latency = 3, TPC = 0) ................................................................................. 727
Synchronous DRAM Write Bus Cycle (RCD = 0, TPC = 0, TRWL = 0)............ 728
Synchronous DRAM Write Bus Cycle (RCD = 2, TPC = 1, TRWL = 1)............ 729
Synchronous DRAM Write Bus Cycle (Burst Write (Single Write × 4),
RCD = 0, TPC = 1, TRWL = 0) ........................................................................... 730
Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write × 4),
RCD = 1, TPC = 0, TRWL = 0) ........................................................................... 731
Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row Address,
CAS Latency = 1)................................................................................................. 732
Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row Address,
CAS Latency = 2)................................................................................................. 733
Synchronous DRAM Burst Read Bus Cycle (RAS Down, Different Row
Address, TPC = 0, RCD = 0, CAS Latency = 1) .................................................. 734
Synchronous DRAM Burst Read Bus Cycle
(RAS Down, Different Row Address, TPC = 1, RCD = 0, CAS Latency = 1) .... 735
Synchronous DRAM Burst Write Bus Cycle (RAS Down, Same Row Address) 736
Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row
Address, TPC = 0, RCD = 0) ............................................................................... 737
Rev. 5.0, 09/03, page xxxix of xlvi