SH7729R Datasheet, PDF (708/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

21.2.2 A/D Control/Status Register (ADCSR)
Bit: 7
6
ADF ADIE
Initial value: 0
0
R/W: R/(W)^* R/W
Note: * Write 0 to clear the flag.
5
ADST
0
R/W
4
MULTI
0
R/W
3
CKS
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
0
CH0
0
R/W
ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter.
ADCSR is initialized to H'00 by a reset and in standby mode.
Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.
Bit 7: ADF
0
1
Description
[Clearing conditions]
(Initial value)
(1) Cleared by reading ADF while ADF = 1, then writing 0 to ADF
(2) Cleared when DMAC is activated by ADI interrupt and ADDR is read
[Setting conditions]
Single mode: A/D conversion ends
Multi mode: A/D conversion ends on all selected channels
Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the
end of A/D conversion.
Bit 6: ADIE
0
1
Description
A/D end interrupt request (ADI) is disabled
A/D end interrupt request (ADI) is enabled
(Initial value)
Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during
A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin.
Bit 5: ADST
0
1
Description
A/D conversion is stopped
(Initial value)
Single mode: A/D conversion starts; ADST is automatically cleared to 0 when
conversion ends
Scan mode: A/D conversion starts and continues, cycling through the selected
channels, until ADST is cleared to 0 by software, by a reset, or by a transition to
standby mode
Rev. 5.0, 09/03, page 662 of 806