SH7729R Datasheet, PDF (201/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

5.5.2 Invalidating a Specific Address
A specific address can be invalidated by writing 0 to the entry’s V bit. When the A bit is 1, the
address tag specified by the write data is compared to the address tag within the cache selected by
the entry address, and data is written when a match is found. If no match is found, there is no
operation. R0 specifies the write data and R1 specifies the address. When the V bit of an entry in
the address array is set to 0, the entry is written back if the entry’s U bit is 1.
; R0=H'01100010; Tag address=B'0000 0001 0001 0000 0000 00, U=0, V=0
; R1=H'F0000088; address array access, entry=H'08, A=1
;
MOV.L R0,@R1
In the following example, an address (32-bit) to be purged is specified in R0.
MOV.L #H'00000FF0, R1 ;
AND R0, R1
; The entry address is fetched.
MOV.L #H'F0000008, R2 ;
OR R1, R2
; The start is set to H'F0 and the A bit
to 1.
MOV.L #H'1FFFFC00, R3 ;
AND R0, R3
; The tag address is fetched. U = V = 0.
MOV.L R3, @R2
; Associative purge.
The above operation should be performed using a non-cacheable area.
5.5.3 Reading the Data of a Specific Entry
This example reads the data section of a specific cache entry. The longword indicated in the data
field of the data array in figure 5.6 is read into the register. R0 specifies the address and R1 is read.
; R1=H'F100 004C; data array access, entry=H'04, Way = 0,
; longword address = 3
;
MOV.L @R0,R1 ; Longword 3 is read.
Rev. 5.0, 09/03, page 155 of 806