SH7729R Datasheet, PDF (245/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

8.2.3 Break Bus Cycle Register A (BBRA)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
7
CDA1
0
R/W
6
CDA0
0
R/W
5
IDA1
0
R/W
4
IDA0
0
R/W
3
RWA1
0
R/W
2
RWA0
0
R/W
1
SZA1
0
R/W
0
SZA0
0
R/W
Break bus cycle register A (BBRA) is a 16-bit readable/writable register that specifies (1) CPU
cycle or DMAC cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size
in the break conditions of channel A. BBRA is initialized to H'0000 by a power-on reset.
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 7 and 6—CPU Cycle/DMAC Cycle Select A (CDA1, CDA0): Select a CPU cycle or
DMAC cycle as the bus cycle of the channel A break condition.
Bit 7: CDA1 Bit 6: CDA0
0
0
*
1
1
0
Note: * Don’t care
Description
Condition comparison is not performed
Break condition is CPU cycle
Break condition is DMAC cycle
(Initial value)
Bits 5 and 4—Instruction Fetch/Data Access Select A (IDA1, IDA0): Select an instruction
fetch cycle or data access cycle as the bus cycle of the channel A break condition.
Bit 5: IDA1
0
1
Bit 4: IDA0
0
1
0
1
Description
Condition comparison is not performed
(Initial value)
Break condition is instruction fetch cycle
Break condition is data access cycle
Break condition is instruction fetch cycle or data access cycle
Rev. 5.0, 09/03, page 199 of 806