SH7729R Datasheet, PDF (732/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

ASEBRKAK: Dedicated emulator pin
23.2.2 Block Diagram
Figure 23.1 shows a block diagram of the UDI.
TDI
SDBPR
SDIR
TDO
MUX
TCK
TMS
TRST
TAP controller
Decoder
Local
bus
Figure 23.1 Block Diagram of UDI
23.3 Register Descriptions
The UDI has the following registers.
• SDBPR: Bypass register
• SDIR: Instruction register
• SDBSR: Boundary scan register
Rev. 5.0, 09/03, page 686 of 806