SH7729R Datasheet, PDF (40/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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Figure D.1
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Figure D.3
Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row
Address, TPC = 1, RCD = 1) ............................................................................... 738
Synchronous DRAM Auto-Refresh Timing (TRAS = 1, TPC = 1) ..................... 739
Synchronous DRAM Self-Refresh Cycle (TRAS = 1, TPC = 1) ......................... 740
Synchronous DRAM Mode Register Write Cycle ............................................... 741
PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait) ............................. 742
PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait,
WAITSEL = 1)..................................................................................................... 743
PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait).......... 744
PCMCIA Memory Bus Cycle (Burst Read, TED = 1, TEH = 1, Two Waits,
Burst Pitch = 3, WAITSEL = 1)........................................................................... 745
PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait)...................................... 746
PCMCIA I/O Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait,
WAITSEL = 1)..................................................................................................... 747
PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, One Wait, Bus Sizing,
WAITSEL = 1)..................................................................................................... 748
TCLK Input Timing ............................................................................................. 750
TCLK Clock Input Timing................................................................................... 750
RTC Crystal Oscillator Oscillation Settling Time at Power-On........................... 750
SCK Input Clock Timing ..................................................................................... 750
SCI I/O Timing in Synchronous Mode ................................................................ 751
I/O Port Timing .................................................................................................... 751
DREQ Input Timing............................................................................................. 752
DRAK Output Timing.......................................................................................... 752
TCK Input Timing................................................................................................ 753
TRST Input Timing (Reset Hold)......................................................................... 753
UDI Data Transfer Timing ................................................................................... 754
ASEMD0 Input Timing........................................................................................ 754
Output Load Circuit.............................................................................................. 755
Load Capacitance vs. Delay Time........................................................................ 756
Package Dimensions (FP-208C)........................................................................... 803
Package Dimensions (FP-208E)........................................................................... 804
Package Dimensions (BP-240A).......................................................................... 805
Rev. 5.0, 09/03, page xl of xlvi