SH7729R Datasheet, PDF (308/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit:
Initial value:
R/W:
7
TME
0
R/W
6
WT/IT
0
R/W
5
RSTS
0
R/W
4
WOVF
0
R/W
3
IOVF
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Bit 7—Timer Enable (TME): Starts and stops timer operation. Clear this bit to 0 when using the
WDT in standby mode or when changing the clock frequency.
Bit 7: TME
0
1
Description
Timer disabled: Count-up stops and WTCNT value is retained
(Initial value)
Timer enabled
Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or an
interval timer.
Bit 6: WT/IT
Description
0
Used as interval timer
(Initial value)
1
Used as watchdog timer
Note: If WT/IT is modified when the WDT is running, the up-count may not be performed correctly.
Bit 5—Reset Select (RSTS): Selects the type of reset when WTCNT overflows in watchdog
timer mode. In interval timer mode, this setting is ignored.
Bit 5: RSTS
Description
0
Power-on reset
1
Manual reset
Note: RESETOUT is output.
(Initial value)
Bit 4—Watchdog Timer Overflow (WOVF): Indicates that the WTCNT has overflowed in
watchdog timer mode. This bit is not set in interval timer mode.
Bit 4: WOVF
0
1
Description
No overflow
WTCNT has overflowed in watchdog timer mode
(Initial value)
Bit 3—Interval Timer Overflow (IOVF): Indicates that WTCNT has overflowed in interval
timer mode. This bit is not set in watchdog timer mode.
Rev. 5.0, 09/03, page 262 of 806