SH7729R Datasheet, PDF (799/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

24.3.9 UDI-Related Pin Timing
Table 24.9 UDI-Related Pin Timing
VccQ = 3.3 ± 0.3 V, Vcc = 1.55 V to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C
Item
TCK cycle time
TCK high pulse width
TCK low pulse width
TCK rise/fall time
TRST setup time
TRST hold time
TDI setup time
TDI hold time
TMS setup time
TMS hold time
TDO delay time
ASEMD0 setup time
ASEMD0 hold time
Symbol
Min
Max Unit Figure
tTCKcyc
50
—
ns
24.55
tTCKH
12
—
ns
tTCKL
12
—
ns
tTCKf
—
4
ns
tTRSTS
12
—
ns
24.56
tTRSTH
50
—
tcyc
tTDIS
10
—
ns
24.57
tTDIH
10
—
ns
tTMSS
10
—
ns
tTMSH
10
—
ns
tTDOD
—
16
ns
tASEMDH
12
—
ns
24.58
tASEMDS
12
—
ns
TCK
(input)
1/2_VcoQ
t_TCKcyc
t_TCKH
t_TCKL
V_IH V_IH
V_IL V_IL
V_IL
1/2_VcoQ
t_TCKf
t_TCKf
Figure 24.55 TCK Input Timing
RESETP
TRST
t_TRSTS
t_TRSTH
Figure 24.56 TRST Input Timing (Reset Hold)
Rev. 5.0, 09/03, page 753 of 806