SH7729R Datasheet, PDF (237/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Number of States
Item
Peripheral
NMI
IRQ
PINT
Modules Notes
Response Total
time
(5.5 + X)
× Icyc
+ 0.5 × Bcyc
+ 0.5 × Pcyc
(5.5 + X)
× Icyc
+ 1 × Bcyc +
4.5 × Pcyc^*4
(5.5 + X)
× Icyc
+ 3.5 ×
Pcyc^*5
(5.5 + X)
× Icyc
+ 1.5
× Pcyc^*5
Minimum 7.5
case^*2
Maximum 8.5 + S
case^*3
16.5
26.5 + S
12.5
18.5 + S
(5.5 + X)
× Icyc
+ 3 × Pcyc^*6
8.5^*5/11.5^*6
10.5 + S^*5
16.5 + S^*6
At 60-MHz (CKIO
= 30) operation:
0.13–0.28 µs
At 60-MHz (CKIO
= 15) operation:
0.26–0.56 µs (in
case of operand
cache-hit)
At 60-MHz (CKIO
= 15) operation:
0.29–0.59 µs
(when external
memory access is
performed with
wait = 0)
Icyc: Duration of one cycle of internal clock supplied to CPU.
Bcyc: Duration of one CKIO cycle.
Pcyc: Duration of one cycle of peripheral clock supplied to peripheral modules.
Notes: 1. S also includes the memory access wait time.
The processing requiring the maximum execution time is LDC.L @Rm+, SR. When the
memory access is a cache-hit, this requires seven instruction execution cycles. When
the external access is performed, the corresponding number of cycles must be added.
There are also instructions that perform two external memory accesses; if the external
memory access is slow, the number of instruction execution cycles will increase
accordingly.
2. The internal clock:CKIO:peripheral clock ratio is 2:1:1.
3. The internal clock:CKIO:peripheral clock ratio is 4:1:1.
4. IRQ mode
5. Modules: TMU, RTC, SCI, WDT, REFC
6. Modules: DMAC, ADC, IrDA, SCIF
Rev. 5.0, 09/03, page 191 of 806