SH7729R Datasheet, PDF(639/855 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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SH7729R Datasheet, PDF (639/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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1

Serial

data

Start

bit

0 D0

Parity Stop Start

Data bit bit bit

D1

D7 0/1 1 0 D0

Parity Stop

Data bit bit

1

D1

D7 0/1

1

Idle (mark)

state

RDF

FER

RXI interrupt

request

One frame

Data read and RDF

flag read as 1 then

cleared to 0 by

RXI interrupt handler

ERI interrupt

request generated

by receive error

Figure 17.11 Example of SCIF Receive Operation

(8-Bit Data, Parity, One Stop Bit)

5. When modem control is enabled, the RTS signal is output when SCFRDR is empty. When

RTS is 0, reception is possible. When RTS is 1, this indicates that SCFRDR is full and

reception is not possible.

Figure 17.12 shows an example of the operation when modem control is used.

Serial

data

RXD

Start

bit

0 D0 D1 D2

Parity bit

D7 0/1 1

Start

0

RTS

Figure 17.12 Example of Operation Using Modem Control (RTS)

Rev. 5.0, 09/03, page 593 of 806

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