SH7729R Datasheet, PDF (306/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

• Bits STC2 to STC0 are not changed.
• The clock ratio is other than Iφ:Bφ = 1:1.
10.6 Overview of WDT
10.6.1 Block Diagram of WDT
Figure 10.2 shows a block diagram of the WDT.
Standby
cancellation
Internal
reset
request
Interrupt
request
Standby
control
WDT
Reset
control
Interrupt
control
Clock selection
Overflow
Divider
Clock selector
Clock
WTCSR
WTCNT
Bus interface
Standby
mode
Peripheral
clock
Legend
WTCSR: Watchdog timer control/status register
WTCNT: Watchdog timer counter
Internal bus
Figure 10.2 Block Diagram of WDT
10.6.2 Register Configuration
The WDT has two registers that select the clock, switch the timer mode, and perform other
functions. Table 10.5 shows the WDT registers.
Rev. 5.0, 09/03, page 260 of 806