SH7729R Datasheet, PDF (289/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

9.6.3 Timing for Canceling Sleep Mode
Sleep to Interrupt
CKIO, CKIO2^*3
STATUS
Normal^*2
Interrupt request
Sleep^*1
Normal^*2
Notes: 1. Sleep: HL (STATUS1 high, STATUS0 low)
2. Normal: LL (STATUS1 low, STATUS0 low)
3. CKIO2 output can only be used in clock modes 0, 1, and 2.
Figure 9.7 Sleep to Interrupt STATUS Output
Sleep to Power-On Reset
Reset
CKIO, CKIO2^*7
RESETP^*1
STATUS
Normal^*5
Sleep^*4 *2
Reset^*3
Normal^*5
0 to 10 Bcyc^*6
0 to 30 Bcyc^*6
Notes: 1. When the PLL1’s multiplication ratio is changed by a power-on reset, keep
RESETP low during the PLL’s oscillation settling time.
2. Undefined
3. Reset: HH (STATUS1 high, STATUS0 high)
4. Sleep: HL (STATUS1 high, STATUS0 low)
5. Normal: LL (STATUS1 low, STATUS0 low)
6. Bcyc: Bus clock cycle
7. CKIO2 output can only be used in clock modes 0, 1, and 2.
Figure 9.8 Sleep to Power-On Reset STATUS Output
Rev. 5.0, 09/03, page 243 of 806