SH7729R Datasheet, PDF (480/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

13.1.2 Block Diagram
Figure 13.1 shows a block diagram of the TMU.
Pφ
TCLK
RTCCLK
Prescaler
Clock
controller
Ch. 0
Counter
controller
Bus interface
TOCR
TSTR
TCR0
TCNT0
TUNI0
Interrupt
controller
Ch. 1
Counter
controller
TCOR0
TCR1
TCNT1
TUNI1
Interrupt
controller
Ch. 2
Counter
controller
TCOR1
TCR2
TCPR2
TCNT2
TUNI2
TICPI2
Legend
TOCR: Timer output control register
TSTR: Timer start register
TCR: Timer control register
Interrupt
controller
TCOR2
TMU
TCNT: 32-bit timer counter
TCOR: 32-bit timer constant register
TCPR2: 32-bit input capture register
Figure 13.1 Block Diagram of TMU
Rev. 5.0, 09/03, page 434 of 806