SH7729R Datasheet, PDF (276/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 7—Standby (STBY): Specifies transition to standby mode.
Bit 7: STBY
0
1
Description
Executing SLEEP instruction puts chip into sleep mode
value)
Executing SLEEP instruction puts chip into standby mode
(Initial
Bits 6, 5, and 3—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 4—Standby Crystal (STBXTL): Specifies halting or operating of the clock pulse generator
in standby mode.
Bit 4: STBXTL
0
1
Description
Clock pulse generator is halted in standby mode
Clock pulse generator is operates in standby mode
Bit 2—Module Standby 2 (MSTP2): Specifies halting of the clock supply to the timer unit TMU
(an on-chip peripheral module). When the MSTP2 bit is set to 1, the supply of the clock to the
TMU is halted.
Bit 2: MSTP2
0
1
Description
TMU runs
Clock supply to TMU is halted
(Initial value)
Bit 1—Module Standby 1 (MSTP1): Specifies halting of the clock supply to the realtime clock
RTC (an on-chip peripheral module). When the MSTP1 bit is set to 1, the supply of the clock to
the RTC is halted. When the clock halts, all RTC registers become inaccessible, but the counter
keeps running.
Bit 1: MSTP1
0
1
Description
RTC runs
Clock supply to RTC is halted
(Initial value)
Before switching the RTC to module standby, access at least one among the registers RTC, SCI,
and TMU.
Bit 0—Module Standby 0 (MSTP0): Specifies halting of the clock supply to the serial
communication interface SCI (an on-chip peripheral module). When the MSTP0 bit is set to 1, the
supply of the clock to the SCI is halted.
Rev. 5.0, 09/03, page 230 of 806