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SH7729R Datasheet, PDF (370/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
Table 11.13 Relationship between Bus Width, AMX Bits, and Address Multiplex Output
Setting
External Address Pins
Bus Memory
Output A1 to
Width Type AMX3 AMX2 AMX1 AMX0 Timing A8 A9
A10 A11 A12 A13 A14 A15 A16
32 bits 4M ×
1
1
0
1
Column A1 to A9 A10 A11 L/H*3 A13 A23 A24*4 A25*4
16 bits ×
4 banks*1
address A8
Row
A10 to A18 A19 A20 A21 A22 A23 A24*4 A25*4
address A17
2M ×
0
1
0
1
Column A1 to A9 A10 A11 L/H*3 A13 A23*4 A24*4
16 bits ×
4 banks*2
address A8
Row
A10 to A18 A19 A20 A21 A22 A23*4 A24*4
address A17
1M ×
0
1
0
0
Column A1 to A9 A10 A11 L/H*3 A13 A22*4 A23*4
16 bits ×
4 banks*2
address A8
Row
A9 to A17 A18 A19 A20 A21 A22*4 A23*4
address A16
2M ×
0
1
0
1
Column A1 to A9 A10 A11 L/H*3 A13 A23*4 A24*4
8 bits ×
4 banks*2
address A8
Row
A10 to A18 A19 A20 A21 A22 A23*4 A24*4
address A17
512k × 32 0
1
1
1
Column A1 to A9 A10 A11 L/H*3 A21*4 A22*4 A15
bits ×
4 banks*2
address A8
Row
A9 to A17 A18 A19 A20 A21*4 A22*4 A23
address A16
16 bits 8M ×
1
1
1
0
Column A1 to A9 A10 L/H*3 A12 A23 A24*4 A25*4
16 bits ×
4 banks*1
address A8
Row
A11 to A19 A20 A21 A22 A23 A24*4 A25*4
address A18
4M ×
1
1
0
1
Column A1 to A9 A10 L/H*3 A12 A22 A23*4 A24*4
16 bits ×
4 banks*2
address A8
Row
A10 to A18 A19 A20 A21 A22 A23*4 A24*4
address A17
2M ×
0
1
0
1
Column A1 to A9 A10 L/H*3 A12 A22*4 A23*4 A24
16 bits ×
4 banks*2
address A8
Row
A10 to A18 A19 A20 A21 A22*4 A23*4 A24
address A17
1M ×
0
1
0
0
Column A1 to A9 A10 L/H*3 A12 A21*4 A22*4 A15
16 bits ×
4 banks*2
address A8
Row
A9 to A17 A18 A19 A20 A21*4 A22*4 A23
address A16
2M ×
0
1
0
1
Column A1 to A9 A10 L/H*3 A12 A22*4 A23*4 A24
8 bits ×
4 banks*2
address A8
Row
A10 to A18 A19 A20 A21 A22*4 A23*4 A24
address A17
Notes: 1. Only RAS3L or CASL is output.
2. When addresses are upper 32 Mbytes, RAS3U or CASU is output.
When addresses are lower 32 Mbytes, RAS3L or CASL is output.
3. L/H is a bit used in the command specification: it is fixed at L or H according to the access mode.
4. Bank address specification.
Rev. 5.0, 09/03, page 324 of 806