SH7729R Datasheet, PDF (187/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

• When the BL bit in the SR register is set to 1, ensure that a TLB-related exception or address
error does not occur at an LDC instruction that updates the SR register and the following
instruction. This will be identified as the occurrence of multiple exceptions, and may initiate
reset processing.
Rev. 5.0, 09/03, page 141 of 806