SH7729R Datasheet, PDF (210/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

7.1.4 Register Configuration
The INTC has the 12 registers listed in table 7.2.
Table 7.2 INTC Registers
Name
Interrupt control register 0
Abbr.
ICR0
R/W
R/W
Initial Value^*1 Address
*²
H'FFFFFEE0
Access
Size
16
Interrupt control register 1
ICR1
R/W H'0000
H'04000010
16
(H'A4000010)^*3
Interrupt control register 2
ICR2
R/W H'0000
H'04000012
16
(H'A4000012)^*3
PINT interrupt enable register PINTER R/W H'0000
H'04000014
16
(H'A4000014)^*3
Interrupt priority register A
IPRA
R/W H'0000
H'FFFFFEE2 16
Interrupt priority register B
IPRB
R/W H'0000
H'FFFFFEE4 16
Interrupt priority register C
IPRC
R/W H'0000
H'04000016
16
(H'A4000016)^*3
Interrupt priority register D
IPRD
R/W H'0000
H'04000018
16
(H'A4000018)^*3
Interrupt priority register E
IPRE
R/W H'0000
H'0400001A
16
(H'A400001A)^*3
Interrupt request register 0
IRR0
R/W H'00
H'04000004
8
(H'A4000004)^*3
Interrupt request register 1
IRR1
R
H'00
H'04000006
8
(H'A4000006)^*3
Interrupt request register 2
IRR2
R
H'00
H'04000008
8
(H'A4000008)^*3
Notes: 1. Initialized by a power-on or manual reset.
2. H'8000 when the NMI pin is high, H'0000 when the NMI pin is low.
3. When address translation by the MMU does not apply, the address in parentheses
should be used.
Rev. 5.0, 09/03, page 164 of 806