SH7729R Datasheet, PDF (20/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

3.3.1 Configuration of the TLB ..................................................................................... 99
3.3.2 TLB Indexing ....................................................................................................... 101
3.3.3 TLB Address Comparison.................................................................................... 102
3.3.4 Page Management Information ............................................................................ 104
3.4 MMU Functions ................................................................................................................ 105
3.4.1 MMU Hardware Management ............................................................................. 105
3.4.2 MMU Software Management............................................................................... 105
3.4.3 MMU Instruction (LDTLB) ................................................................................. 106
3.4.4 Avoiding Synonym Problems............................................................................... 107
3.5 MMU Exceptions .............................................................................................................. 110
3.5.1 TLB Miss Exception ............................................................................................ 110
3.5.2 TLB Protection Violation Exception.................................................................... 111
3.5.3 TLB Invalid Exception......................................................................................... 112
3.5.4 Initial Page Write Exception ................................................................................ 113
3.5.5 Processing Flow in Event of MMU Exception
(Same Processing Flow for Address Error) .......................................................... 115
3.5.6 MMU Exception in Repeat Loop ......................................................................... 117
3.6 Memory-Mapped TLB ...................................................................................................... 118
3.6.1 Address Array ...................................................................................................... 118
3.6.2 Data Array ............................................................................................................ 119
3.6.3 Usage Examples ................................................................................................... 121
3.7 Usage Note ........................................................................................................................ 121
Section 4 Exception Handling.......................................................................................... 123
4.1 Overview ........................................................................................................................... 123
4.1.1 Features ................................................................................................................ 123
4.1.2 Register Configuration ......................................................................................... 123
4.2 Exception Handling Function............................................................................................ 123
4.2.1 Exception Handling Flow..................................................................................... 123
4.2.2 Exception Vector Addresses................................................................................. 124
4.2.3 Acceptance of Exceptions .................................................................................... 126
4.2.4 Exception Codes................................................................................................... 128
4.2.5 Exception Request Masks .................................................................................... 129
4.2.6 Returning from Exception Handling .................................................................... 129
4.3 Register Descriptions......................................................................................................... 130
4.4 Exception Handling Operation .......................................................................................... 131
4.4.1 Reset..................................................................................................................... 131
4.4.2 Interrupts .............................................................................................................. 131
4.4.3 General Exceptions............................................................................................... 132
4.5 Individual Exception Operations ....................................................................................... 132
4.5.1 Resets ................................................................................................................... 132
4.5.2 General Exceptions............................................................................................... 133
4.5.3 Interrupts .............................................................................................................. 138
Rev. 5.0, 09/03, page xx of xlvi