SH7729R Datasheet, PDF (795/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

24.3.8 Peripheral Module Signal Timing
Table 24.8 Peripheral Module Signal Timing
VccQ = 3.3 ± 0.3 V, Vcc = 1.55 V to 2.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C
Module
TMU,
RTC
SCI
Port
Item
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
Edge specification
Both-edge specification
Oscillation settling time
Input clock
cycle
Asynchronous
Synchronous
Input clock rise time
Input clock fall time
Input clock pulse width
Transmit data delay time
Receive data setup time (synchronous)
Receive data hold time (synchronous)
RTS delay time
CTS setup time (synchronous)
CTS hold time (synchronous)
Output data delay time
Input data setup time
Input data hold time
Input data setup time
Input data hold time
Input data setup time
Input data hold time
DMAC DREQ setup time
DREQ hold time
DRAK delay time
Note: * pcyc is the P clock cycle.
Symbol Min Max
tTCLKS
15
—
tTCKS
15
—
tTCKWH 1.5
—
tTCKWL 2.5
—
tROSC
3
—
tSCYC
4
—
6
—
tSCKR
tSCKF
tSCKW
tTXD
tRXS
tRXH
tRTSD
tCTSS
tCTSH
tPORTD
tPORTS1
tPORTH1
tPORTS2
—
—
0.4
—
100
100
—
100
100
—
15
8
tcyc +
15
1.5
1.5
0.6
100
—
—
100
—
—
17
—
—
—
tPORTH2
tPORTS3
8
—
3 × tcyc —
+ 15
tPORTH3 8
—
tDRES
6
—
tDREQH 4
—
tDRAKD
—
10
Unit Figure
ns 24.47
24.48
pcyc^*
S
24.49
pcyc^* 24.50,
24.51
24.50
tscyc
ns 24.51
ns 24.52
ns 24.53
24.54
Rev. 5.0, 09/03, page 749 of 806