SH7729R Datasheet, PDF (208/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

7.1.2 Block Diagram
Figure 7.1 shows a block diagram of the INTC.
IRQOUT
NMI
IRL3−IRL0
IRLS3−IRLS0
IRQ0−IRQ5
PINT0−PINT15
DMAC
IrDA
SCIF
SCI
ADC
TMU
RTC
WDT
REF
UDI
4 _Input/output
4
control
6
16
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request/
refresh request)
(Interrupt request)
Priority
identifier
Com-
parator
Interrupt
request
SR
3210
CPU
ICR
IPR
IPRA−IPRE
Legend
TMU
: Timer unit
RTC
: Realtime clock unit
SCI
: Serial communication interface
IrDA
: Serial communication interface (with IrDA)
SCIF
: Serial communication interface (with FIFO)
WDT
: Watchdog timer
REF
: Refresh requests in the bus state controller
ICR
: Interrupt control register
IPRA−IPRE : Interrupt priority registers A−E
SR
: Status register
DMAC : Direct memory access controller
ADC
: Analog-to-digital converter
UDI
: User debugging interface
Bus
interface
INTC
Figure 7.1 Block Diagram of INTC
Rev. 5.0, 09/03, page 162 of 806