SH7729R Datasheet, PDF (442/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

CKIO
A25 to A0
CSn
D31 to D0
RD
WEn
DACKn
Transfer source
address
Data read cycle
Transfer destination
address
Data write cycle
(1st cycle)
(2nd cycle)
Note: In transfer between external memories, with DACK output in the read cycle, DACK
output timing is the same as that of CSn.
Figure 12.6 Example of DMA Transfer Timing in the Direct Address Mode in Dual Mode
(Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory)
Rev. 5.0, 09/03, page 396 of 806