SH7729R Datasheet, PDF (719/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 21.4 A/D Conversion Time (Single Mode)
CKS = 0
Symbol Min
Typ Max
Min
A/D conversion start tD
delay
17
—
28
10
Input sampling time
tSPL
—
129 —
—
A/D conversion time
tCONV
514
—
525
259
Note: Values in the table are numbers of states (tcyc).
CKS = 1
Typ
Max
—
17
65
—
—
266
21.4.5 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGE1 and TRGE0 bits are set to 1 in
ADCR, external trigger input is enabled at the ADTRG pin. A high-to-low transition at the
ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations,
regardless of the conversion mode, are the same as if the ADST bit had been set to 1 by software.
Figure 21.7 shows the timing.
Pφ
ADTRG
External
trigger signal
ADST
A/D conversion
Figure 21.7 External Trigger Input Timing
Rev. 5.0, 09/03, page 673 of 806