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SH7729R Datasheet, PDF (123/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series | |||
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Table 2.28 Single Data Transfer Instructions
Instruction
Instruction Code
Operation
Execu-
tion
DC
States
MOVS.W @-As,Ds
111101AADDDD0000 As â 2 â As, (As) â
1
â
MSW of Ds, 0 â LSW of Ds
MOVS.W @As,Ds
111101AADDDD0100 (As) â MSW of Ds,
0 â LSW of Ds
1
â
MOVS.W @As+,Ds
111101AADDDD1000 (As) â MSW of Ds,
1
â
0 â LSW of Ds, As + 2 â As
MOVS.W @As+Ix,Ds 111101AADDDD1100 (Asc) â MSW of Ds,
1
â
0 â LSW of Ds, As + Ix â As
MOVS.W Ds,@-As*
111101AADDDD0001 As â 2 â As,
MSW of Ds â (As)
1
â
MOVS.W Ds,@As*
111101AADDDD0101 MSW of Ds â (As)
1
â
MOVS.W Ds,@As+*
111101AADDDD1001 MSW of Ds â (As),
As + 2 â As
1
â
MOVS.W Ds,@As+Ix* 111101AADDDD1101 MSW of Ds â (As),
As + Ix â As
1
â
MOVS.L @-As,Ds
111101AADDDD0010 As â 4 â As, (As) â Ds
1
â
MOVS.L @As,Ds
111101AADDDD0110 (As) â Ds
1
â
MOVS.L @As+,Ds
111101AADDDD1010 (As) â Ds, As + 4 â As
1
â
MOVS.L @As+Ix,Ds 111101AADDDD1110 (As) â Ds, As + Ix â As
1
â
MOVS.L Ds,@-As
111101AADDDD0011 As â 4 â As, Ds â (As)
1
â
MOVS.L Ds,@As
111101AADDDD0111 Ds â (As)
1
â
MOVS.L Ds,@As+
111101AADDDD1011 Ds â (As), As + 4 â As
1
â
MOVS.L Ds,@As+Ix 111101AADDDD1111 Ds â (As), As + Ix â As
1
â
Note: * If guard bit registers A0G and A1G are specified in source operand Ds, the data is output
to the LDB[7:0] bus and the sign bit is copied into the upper bits, [31:8].
Rev. 5.0, 09/03, page 77 of 806
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