SH7729R Datasheet, PDF (333/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bits 2n + 1, 2n—Area n (6–2, 0) Intercycle Idle Specification (AnIW1, AnIW0): Specify the
number of idles inserted between bus cycles when switching between physical space area n (6–2,
0) and another space or between a read access and a write access in the same physical space.
Bit 2n + 1: AnIW1
0
1
Bit 2n: AnIW0
0
1
0
1
Description
1 idle cycle inserted
1 idle cycle inserted
2 idle cycles inserted
3 idle cycles inserted
(Initial value)
11.2.4 Wait State Control Register 2 (WCR2)
Wait state control register 2 (WCR2) is a 16-bit readable/writable register that specifies the
number of wait state cycles inserted for each area. It also specifies the data access pitch for burst
memory accesses. This allows direct connection of even low-speed memories without an external
circuit. WCR2 is initialized to H'FFFF by a power-on reset. It is not initialized by a manual reset
or in standby mode.
Bit:
Initial value:
R/W:
15
A6 W2
1
R/W
14
A6 W1
1
R/W
13
A6 W0
1
R/W
12
A5 W2
1
R/W
11
A5 W1
1
R/W
10
A5 W0
1
R/W
9
A4 W2
1
R/W
8
A4 W1
1
R/W
Bit:
Initial value:
R/W:
7
A4 W0
1
R/W
6
A3 W1
1
R/W
5
A3 W0
1
R/W
4
A2 W1
1
R/W
3
A2 W0
1
R/W
2
A0 W2
1
R/W
1
A0 W1
1
R/W
0
A0 W0
1
R/W
Rev. 5.0, 09/03, page 287 of 806