SH7729R Datasheet, PDF (762/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

24.3.3 AC Bus Timing
Table 24.7 Bus Timing
Clock Modes 0/1/2/7, VccQ = 3.3 ± 0.3 V, Vcc = 1.55 V to 2.15 V, AVcc = 3.3 ± 0.3 V,
Ta = –20 to 75°C
Item
Symbol Min Max Unit Figure
Address delay time
Address setup time
Address hold time ^*1
BS delay time
CS delay time 1
CS delay time 2
CS delay time 3
(SDRAM access)
tAD
tAS
tAH
tBSD
tCSD1
tCSD3
tCSD3
1.5 12 ns 24.16–24.36, 24.39–24.46
0 — ns 24.16–24.18
4 — ns 24.16–24.21
— 10 ns 24.16–24.36, 24.39–24.46
— 10 ns 24.16–24.36, 24.39–24.46
— 10 ns 24.16–24.21
1.5 10 ns 24.22–24.39
Read/write delay time tRWD
Read/write hold time
tRWH
Read strobe delay time tRSD
Read data setup time 1 tRDS1
Read data setup time 2 tRDS2
Read data hold time 1 ^*2 tRDH1
Read data hold time 2 tRDH2
Write enable delay time tWED
Write data delay time 1 tWDD1
Write data delay time 2 tWDD2
Write data hold time 1 tWDH1
Write data hold time 2 tWDH2
Write data hold time 3 tWDH3
Write data hold time 4 tWDH4
WAIT setup time
tWTS
WAIT hold time
tWTH
RAS delay time 2
tRASD2
CAS delay time 2
tCASD2
DQM delay time
tDQMD
CKE delay time
tCKED
1.5 10 ns 24.16–24.36, 24.39–24.46
0 — ns 24.16–24.21
— 10 ns 24.16–24.21, 24.40–24.43
6 — ns 24.16–24.21, 24.40–24.46
5 — ns 24.22–24.25, 24.30–24.33
0 — ns 24.16–24.25, 24.40–24.46
1 — ns 24.22–24.25, 24.30–24.33
— 10 ns 24.16–24.18, 24.40, 24.41
— 14 ns 24.16–24.18, 24.40, 24.41, 24.44–24.46
1.5 12 ns 24.26–24.29, 24.34–24.36
1.5 — ns 24.16–24.18, 25.40, 25.41, 24.44–24.46
1.5 — ns 24.26–24.29, 24.34–24.36
2 — ns 24.16–24.18
2 — ns 24.40, 24.41, 24.44–24.46
5 — ns 24.17–24.21, 24.41, 24.43, 24.45, 24.46
0 — ns 24.17–24.21, 24.41, 24.43, 24.45, 24.46
1.5 10 ns 24.22–24.39
1.5 10 ns 24.22–24.39
1.5 10 ns 24.22–24.36
1.5 10 ns 24.38
Rev. 5.0, 09/03, page 716 of 806