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SH7729R Datasheet, PDF (238/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series | |||
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Interrupt
acceptance
Start of interrupt
handling
0.5 Ã Icyc
+ 0.5 Ã Bcyc
+ 2 Ã Pcyc
IRL
5 Ã Icyc
Instruction (instruction
replaced by interrupt
exception handling)
Overrun fetch
IF ID EX EX EX EX
IF
First instruction of interrupt
handler
IF ID EX
IF: Instruction fetch: Instruction is fetched from memory in which program is stored.
ID: Instruction decode: Fetched instruction is decoded.
EX: Instruction execution: Data operation and address calculation are performed.
Figure 7.4 Example of Pipeline Operations when IRL Interrupt is Accepted
Rev. 5.0, 09/03, page 192 of 806
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