SH7729R Datasheet, PDF (647/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Figures 18.2 to 18.4 show the IrDA I/O port pins.
SCIF pin I/O and data control is performed by bits 7 to 4 of SCPCR and bits 3 and 2 of SCPDR.
For details, see section 15.2.8, SC Port Control Register (SCPCR)/SC Port Data Register
(SCPDR).
SCPT[3]/SCK1
Reset
R
D
SCP3MD0
Q
C
PCRW
Reset
R
QD
SCP3MD1
C
PCRW
Reset
R
QD
SCP3DT1
C
PDRW
Internal data bus
IrDA
Clock input enable
Output enable
Serial clock output
PDRR^*
Serial clock input
Legend
PDRW: SCPDR write
PDRR: SCPDR read
PCRW: SCPCR write
Note: * When reading the SCK1 pin, the CKE1 and CKE0 bits in SCSCR to 0, and
set the SCP3MD1 bit in SCSPR to 1 (see section 15.2.8, SC Port Control
Register (SCPCR)/SC Port Data Register (SCPDR)).
Figure 18.2 SCPT[3]/SCK1 Pin
Rev. 5.0, 09/03, page 601 of 806