SH7729R Datasheet, PDF (254/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bits 31 to 22—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 21—Break ASID Mask A (BASMA): Specifies whether or not channel A break bits ASID7
to ASID0 (BASA7 to BASA0) set in BASRA are masked.
Bit 21: BASMA Description
0
All BASRA bits are included in break condition, ASID is checked (Initial value)
1
No BASRA bits are included in break condition, ASID is not checked
Bit 20—Break ASID Mask B (BASMB): Specifies whether or not channel B break bits ASID7
to ASID0 (BASB7 to BASB0) set in BASRB are masked.
Bit 20: BASMB Description
0
All BASRB bits are included in break condition, ASID is checked (Initial value)
1
No BASRB bits are included in break condition, ASID is not checked
Bits 19 to 16—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 15—CPU Condition Match Flag A (SCMFCA): When the CPU bus cycle condition in the
break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to
clear this flag, write 0 to this bit.
Bit 15:
SCMFCA
0
1
Description
CPU cycle condition for channel A is not matched
CPU cycle condition for channel A is matched
(Initial value)
Bit 14—CPU Condition Match Flag B (SCMFCB): When the CPU bus cycle condition in the
break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to
clear this flag, write 0 to this bit.
Bit 14:
SCMFCB
0
1
Description
CPU cycle condition for channel B is not matched
CPU cycle condition for channel B is matched
(Initial value)
Rev. 5.0, 09/03, page 208 of 806