SH7729R Datasheet, PDF (239/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Section 8 User Break Controller
8.1 Overview
The user break controller (UBC) provides functions that simplify program debugging. Break
conditions are set in the UBC and a user break is generated according to the conditions of the bus
cycle generated by the CPU or on-chip DMAC. The breakpoint check function monitors
instruction fetches and operand read/writes, generating a variable combination of pre-execution
instruction fetch, post-execution instruction fetch, and post-execution operand access breakpoint
traps under designated read/write conditions.
This function makes it easy to design an effective self-monitoring debugger, enabling the chip to
debug programs without using an in-circuit emulator.
8.1.1 Features
The UBC has the following features:
• The following break comparison conditions can be set.
Number of break channels: two channels (channels A and B)
User break can be requested as either the independent or sequential condition on channels A
and B (sequential break setting: when a channel A break condition match is followed by a
channel B break condition match, and both matches do not occur in the same bus cycle).
 Address (Compares 40 bits comprising a 32-bit logical address prefixed with an ASID
address. Comparison bits are maskable in 32-bit units; user can mask addresses at lower 12
bits (4-k page), lower 10 bits (1-k page), or any size of page, etc.)
One of four address buses (logic address bus (LAB), internal address bus (IAB),
X-memory address bus (XAB), or Y-memory address bus (YAB)) can be selected.
 Data (only on channel B, 32-bit maskable)
One of the four data buses (logic data bus (LDB), internal data bus (IDB), X-memory data
bus (XDB), or Y-memory data bus (YDB)) can be selected.
 Bus master: CPU or DMAC cycle
 Bus cycle: Instruction fetch or data access
 Read/write
 Operand size: Byte, word, or longword
• User break is generated upon satisfying break conditions. A user-designed user-break
condition exception handling routine can be run.
• In an instruction fetch cycle, break setting before or after instruction execution can be set.
• Breaks can be specified for on-chip I/O accesses or LDTLB instruction execution in ASE
mode.
Rev. 5.0, 09/03, page 193 of 806