SH7729R Datasheet, PDF (259/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

8.2.12 Branch Destination Register (BRDR)
Bit: 31
30
29
28
DVF
—
—
—
Initial value: 0
*
*
*
R/W: R
R
R
R
27
BDA27
*
R
26
BDA26
*
R
25
BDA25
*
R
24
BDA24
*
R
Bit:
Initial value:
R/W:
23
BDA23
*
R
22
BDA22
*
R
21
BDA21
*
R
20
BDA20
*
R
19
BDA19
*
R
18
BDA18
*
R
17
BDA17
*
R
16
BDA16
*
R
Bit:
Initial value:
R/W:
15
BDA15
*
R
14
BDA14
*
R
13
BDA13
*
R
12
BDA12
*
R
11
BDA11
*
R
10
BDA10
*
R
9
BDA9
*
R
8
BDA8
*
R
Bit:
Initial value:
R/W:
Note: * Undefined
7
BDA7
*
R
6
BDA6
*
R
5
BDA5
*
R
4
BDA4
*
R
3
BDA3
*
R
2
BDA2
*
R
1
BDA1
*
R
0
BDA0
*
R
BRDR is a 32-bit read-only register that stores the branch destination fetch address. BRDR has a
flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 when BRDR is read, and
is also initialized by a power-on reset or manual reset. Other bits are not initialized by a reset. Four
BRDR registers have a queue structure, and the stored register is shifted every branch.
Bit 31—BRDR Valid Flag (DVF): Indicates whether a branch destination address is stored.
When a branch destination address is fetched, this flag is set to 1. This flag is set to 0 by reading
BRDR.
Bit 31: DVF
0
1
Description
BRDR register value is invalid
BRDR register value is valid
(Initial value)
Bits 30 to 28—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 27 to 0—Branch Destination Address (BDA27 to BDA0): These bits store the first address
fetched after a branch.
Rev. 5.0, 09/03, page 213 of 806