SH7729R Datasheet, PDF(182/855 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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SH7729R Datasheet, PDF (182/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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ï£§ Operations: The virtual address (32 bits) that caused the exception is set in TEA. PC and

SR of the instruction that generated the exception are saved to SPC and SSR, respectively.

If the exception occurred during a read, H'0E0 is set in EXPEVT; if the exception occurred

during a write, H'100 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a

branch occurs to PC = VBR + H'0100. See section 3.5.5, Processing Flow in Event of

MMU Exception, for more information.

â¢ Unconditional trap

ï£§ Conditions: TRAPA instruction executed

ï£§ Operations: The exception is a processing-completion type, so PC of the instruction after

the TRAPA instruction is saved to SPC. SR from the time when the TRAPA instruction

was executing is saved to SSR. The 8-bit immediate value in the TRAPA instruction is

quadrupled and set in TRA (9â0). H'160 is set in EXPEVT. The BL, MD, and RB bits in

SR are set to 1 and a branch occurs to PC = VBR + H'0100.

â¢ Illegal general instruction exception

ï£§ Conditions:

a. When undefined code not in a delay slot is decoded

Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S,

BF/S

Undefined instruction: H'Fxxx

b. When a privileged instruction not in a delay slot is decoded in user mode

Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access

GBR with LDC/STC are not privileged instructions and therefore do not apply.

c. When a DSP instruction not in a delay slot is decoded without DSP extension

(SR.DSP=0)

DSP instructions: LDS Rm, DSR/A0/X0/X1/Y0/Y1, LDS.L @Rm+,

DSR/A0/X0/X1/Y0/Y1, STS DSR/A0/X0/X1/Y0/Y1,

Rn, STS.L DSR/A0/X0/X1/Y0/Y1, @-Rn, LDC Rm,

RS/RE/MOD, LDC.L @Rm+, RS/RE/MOD,

STC RS/RE/MOD, Rn, STC.L RS/RE/MOD, @-Rn,

LDRS, LDRE, SETRC, MOVS, MOVX, MOVY, Pxxx

d. When an instruction that rewrites PC/SR/RS/RE in the last three instructions of repeat

loop is decoded.

Instructions that rewrite PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE,

BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR,

LDC.L @Rm+, SR

Instructions that rewrite SR: LDC Rm, SR, LDC.L @Rm+, SR, SETRC

Instructions that rewrite RS: LDC Rm, RS, LDC.L @Rm+, RS, LDRS

Instructions that rewrite RE: LDC Rm, RE, LDC.L @Rm+, RE, LDRE

Rev. 5.0, 09/03, page 136 of 806

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