SH7729R Datasheet, PDF (248/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

8.2.5 Break Address Mask Register B (BAMRB)
Bit: 31
30
29
28
27
26
25
24
BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 BAMB24
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23
22
21
20
19
18
17
16
BAMB23 BAMB22 BAMB21 BAMB20 BAMB19 BAMB18 BAMB17 BAMB16
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
14
13
12
11
10
9
8
BAMB15 BAMB14 BAMB13 BAMB12 BAMB11 BAMB10 BAMB9 BAMB8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
BAMB7 BAMB6 BAMB5 BAMB4 BAMB3 BAMB2 BAMB1 BAMB0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
BAMRB is a 32-bit readable/writable register that specifies bits masked in the break address
specified by BARB. BAMRB is initialized to H'00000000 by a power-on reset.
XYE = 0
XYE = 1
BAMB31–16
Mask L(I) AB31–16
Mask XAB15–1 (XYS = 0)
BAMB15–0
Mask L(I) AB15–0
Mask YAB15–1 (XYS = 1)
Bits 31–0:
BAMBn
0
1
n = 31–0
Description
Break address BABn of channel B is included in the break condition (Initial value)
Break address BABn of channel B is masked and is not included in the break
condition
Rev. 5.0, 09/03, page 202 of 806