SH7729R Datasheet, PDF (329/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bits 10 and 9—Area 0 Burst ROM Control (A0BST1, A0BST0): Specify whether to use burst
ROM in physical space area 0. When burst ROM is used, these bits set the number of burst
transfers.
Bit 10: A0BST1
0
Bit 9: A0BST0
0
1
1
0
1
Description
Access area 0 accessed as ordinary memory
(Initial value)
Access area 0 accessed as burst ROM (4 consecutive
accesses). Can be used when bus width is 8, 16, or 32
Access area 0 accessed as burst ROM (8 consecutive
accesses). Can be used only when bus width is 8 or 16.
Bus width of 32 should not be selected when this setting
is used
Access area 0 accessed as burst ROM (16 consecutive
accesses). Can be used only when bus width is 8. Bus
width of 16 or 32 should not be selected when this
setting is used
Bits 8 and 7—Area 5 Burst Enable (A5BST1, A5BST0): Specify whether to use burst ROM
and PCMCIA burst mode in physical space area 5. When burst ROM and PCMCIA burst mode
are used, these bits set the number of burst transfers.
Bit 8: A5BST1
0
1
Bit 7: A5BST0
0
1
0
1
Description
Access area 5 accessed as ordinary memory
(Initial value)
Burst access of area 5 (4 consecutive accesses). Can
be used when bus width is 8, 16, or 32
Burst access of area 5 (8 consecutive accesses). Can
be used only when bus width is 8 or 16. Bus width of 32
should not be selected when this setting is used
Burst access of area 5 (16 consecutive accesses). Can
be used only when bus width is 8. Bus width of 16 or 32
should not be selected when this setting is used
Bits 6 and 5—Area 6 Burst Enable (A6BST1, A6BST0): Specify whether to use burst ROM
and PCMCIA burst mode in physical space area 6. When burst ROM and PCMCIA burst mode
are used, these bits set the number of burst transfers.
Rev. 5.0, 09/03, page 283 of 806