SH7729R Datasheet, PDF(43/855 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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SH7729R Datasheet, PDF (43/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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Table 11.14 Example of Correspondence between SH7729R and Synchronous DRAM

Address Pins (AMX2â0 = 011 (32-Bit Bus Width)) .............................................. 325

Table 11.15 MCSCRx Settings and MCS[x] Assertion Conditions (x: 0â7).............................. 367

Table 12.1 DMAC Pins ............................................................................................................ 372

Table 12.2 DMAC Registers .................................................................................................... 373

Table 12.3 Selecting External Request Modes with RS Bits .................................................... 389

Table 12.4 Selecting On-Chip Peripheral Module Request Modes with RS Bits ..................... 390

Table 12.5 Supported DMA Transfers...................................................................................... 394

Table 12.6 Relationship between Request Modes and Bus Modes by DMA Transfer

Category.................................................................................................................. 405

Table 12.7 Register Configuration............................................................................................ 421

Table 12.8 Transfer Conditions and Register Settings for Transfer between On-Chip SCI

and External Memory ............................................................................................. 427

Table 12.9 Transfer Conditions and Register Settings for Transfer between On-Chip A/D

Converter and External Memory ............................................................................ 428

Table 12.10 Values in DMAC after End of Fourth Transfer ...................................................... 429

Table 12.11 Transfer Conditions and Register Settings for Transfer between External

Memory and SCIF Transmitter............................................................................... 430

Table 13.1 TMU Pin ............................................................................................................... 435

Table 13.2 TMU Registers........................................................................................................ 435

Table 13.3 TMU Interrupt Sources........................................................................................... 449

Table 14.1 RTC Pins................................................................................................................. 453

Table 14.2 RTC Registers......................................................................................................... 454

Table 14.3 Day-of-Week Codes (RWKCNT) .......................................................................... 457

Table 14.4 Day-of-Week Codes (RWKAR) ............................................................................. 461

Table 14.5 Recommended Oscillator Circuit Constants (Recommended Values).................... 469

Table 15.1 SCI Pins .................................................................................................................. 475

Table 15.2 SCI Registers .......................................................................................................... 476

Table 15.3 SCSMR Settings ..................................................................................................... 490

Table 15.4 Bit Rates and SCBRR Settings in Asynchronous Mode ......................................... 490

Table 15.5 Bit Rates and SCBRR Settings in Synchronous Mode ........................................... 494

Table 15.6 Maximum Bit Rates for Various Frequencies with Baud Rate Generator

(Asynchronous Mode) ............................................................................................ 495

Table 15.7 Maximum Bit Rates with External Clock Input (Asynchronous Mode)................. 496

Table 15.8 Maximum Bit Rates with External Clock Input (Synchronous Mode) ................... 496

Table 15.9 Serial Mode Register Settings and SCI Communication Formats .......................... 498

Table 15.10 SCSMR and SCSCR Settings and SCI Clock Source Selection ............................. 498

Table 15.11 Serial Communication Formats (Asynchronous Mode) ......................................... 500

Table 15.12 Receive Error Conditions and SCI Operation......................................................... 508

Table 15.13 SCI Interrupt Sources ............................................................................................. 528

Table 15.14 SCSSR Status Flags and Transfer of Receive Data ................................................ 529

Table 16.1 Smart Card Interface Pins ....................................................................................... 535

Table 16.2 Registers ................................................................................................................. 535

Rev. 5.0, 09/03, page xliii of xlvi

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