SH7729R Datasheet, PDF (637/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

1. Whether a framing error or parity error has occurred in the receive data read from SCFRDR
can be ascertained from the FER and PER bits in SCSSR.
2. When a break signal is received, receive data is not transferred to SCFRDR while the BRK
flag is set. However, note that the last data in SCFRDR is H'00 and the break data in which a
framing error occurred is stored.
Error handling
No
ER = 1?
Yes
Receive error handling
No
BRK = 1?
Break processing
No
DR = 1?
Yes
Read receive data from SCFRDR
Clear DR, ER, BRK flags in
SCSSR to 0
End
Figure 17.10 Sample Flowchart for Receiving Serial Data (cont)
Rev. 5.0, 09/03, page 591 of 806