SH7729R Datasheet, PDF (209/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

7.1.3 Pin Configuration
Table 7.1 shows the INTC pin configuration.
Table 7.1 INTC Pins
Name
Abbreviation I/O
Nonmaskable interrupt input NMI
I
pin
Interrupt input pins
Port interrupt input pins
IRQ5–IRQ0
I
IRL3–IRL0
IRLS3–IRLS0
PINT0–PINT15 I
Interrupt request output pin IRQOUT
O
Description
Input of interrupt request signal, not
maskable by the interrupt mask bits in
SR
Input of interrupt request signals,
maskable by the interrupt mask bits in
SR
Input of port interrupt request signals,
maskable by the interrupt mask bits in
SR
Output of signal that notifies external
devices that an interrupt source or
memory refresh has occurred
Rev. 5.0, 09/03, page 163 of 806