SH7729R Datasheet, PDF (307/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 10.5 Register Configuration
Name
Abbreviation R/W Access Size Initial Value Address
Watchdog timer counter WTCNT
R/W^* R: byte;
W: word^*
H'00
H'FFFFFF84
Watchdog timer
control/status register
WTCSR
R/W^* R: byte;
W: word^*
H'00
H'FFFFFF86
Note: * Write with word access. Write with H'5A and H'A5, respectively, in the upper byte. Byte or
longword writes are not possible. Read with byte access.
10.7 WDT Registers
10.7.1 Watchdog Timer Counter (WTCNT)
The watchdog timer counter (WTCNT) is an 8-bit readable/writable counter that increments on the
selected clock. WTCNT differs from other registers in that it is more difficult to write to. See
section 10.7.3, Notes on Register Access, for details. When an overflow occurs, it generates a reset
in watchdog timer mode and an interrupt in interval time mode. Its address is H'FFFFFF84. The
WTCNT counter is initialized to H'00 only by a power-on reset through the RESETP pin. Use
word access to write to the WTCNT counter, with H'5A in the upper byte. Use byte access to read
WTCNT.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
10.7.2 Watchdog Timer Control/Status Register (WTCSR)
The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register
composed of bits to select the clock used for the count, bits to select the timer mode, and overflow
flags. WTCSR differs from other registers in that it is more difficult to write to. See section 10.7.3,
Notes on Register Access, for details. Its address is H'FFFFFF86. The WTCSR register is
initialized to H'00 only by a power-on reset through the RESETP pin. When a WDT overflow
causes an internal reset, WTCSR retains its value. When used to count the clock settling time for
canceling a standby, it retains its value after counter overflow. Use word access to write to the
WTCSR counter, with H'A5 in the upper byte. Use byte access to read WTCSR.
Note: The method of writing data to this register differs from that for ordinary registers in order
to ensure that data is not overwritten mistakenly. Refer to section 10.7.3, Notes on
Register Access, for details.
Rev. 5.0, 09/03, page 261 of 806