SH7729R Datasheet, PDF (319/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Pin Name
Data enable 3
Signal
I/O
WE3/DQMUU/ O
ICIOWR
Read
RD
O
Wait
WAIT
I
Clock enable
CKE
O
IOIS16
IOIS16
I
Bus release
request
Bus release
acknowledgment
Mask ROM chip
select
BREQ
I
BACK
O
MCS[0]–MCS[7] O
Description
When memory other than synchronous DRAM and
PCMCIA is used, D31–D24 write strobe signal.
When synchronous DRAM is used, selects D31–
D24. When PCMCIA is used, strobe signal
indicating I/O write.
Strobe signal indicating read cycle
Wait state request signal
Clock enable control signal for synchronous DRAM
Signal indicating PCMCIA 16-bit I/O. Valid only in
little-endian mode.
Bus release request signal
Bus release acknowledge signal
Chip select signal for mask ROM connected to area
0 or 2.
Rev. 5.0, 09/03, page 273 of 806