SH7729R Datasheet, PDF (19/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Contents
Section 1 Overview ............................................................................................................. 1
1.1 Features ............................................................................................................................. 1
1.2 Block Diagram .................................................................................................................. 7
1.3 Pin Description .................................................................................................................. 8
1.3.1 Pin Assignment .................................................................................................... 8
1.3.2 Pin Function ......................................................................................................... 10
Section 2 CPU....................................................................................................................... 19
2.1 Registers ............................................................................................................................ 19
2.1.1 General Registers ................................................................................................. 23
2.1.2 Control Registers.................................................................................................. 25
2.1.3 System Registers .................................................................................................. 30
2.1.4 DSP Registers....................................................................................................... 30
2.2 Data Formats ..................................................................................................................... 35
2.2.1 Register Data Format (Non-DSP Type) ............................................................... 35
2.2.2 DSP-Type Data Formats ...................................................................................... 35
2.2.3 Memory Data Formats.......................................................................................... 37
2.3 Features of CPU Core Instructions .................................................................................... 37
2.4 Instruction Formats............................................................................................................ 41
2.4.1 CPU Instruction Addressing Modes ..................................................................... 41
2.4.2 DSP Data Addressing........................................................................................... 45
2.4.3 CPU Instruction Formats...................................................................................... 49
2.4.4 DSP Instruction Formats ...................................................................................... 53
2.5 Instruction Set.................................................................................................................... 59
2.5.1 CPU Instruction Set.............................................................................................. 59
2.6 DSP Extended-Function Instructions ................................................................................ 73
2.6.1 Introduction .......................................................................................................... 73
2.6.2 Added CPU System Control Instructions............................................................. 73
2.6.3 Single and Double Data Transfer for DSP Data Instructions ............................... 75
2.6.4 DSP Operation Instruction Set ............................................................................. 79
Section 3 Memory Management Unit (MMU)............................................................ 91
3.1 Overview ........................................................................................................................... 91
3.1.1 Features ................................................................................................................ 91
3.1.2 Role of MMU ....................................................................................................... 91
3.1.3 SH7729R MMU ................................................................................................... 94
3.1.4 Register Configuration ......................................................................................... 97
3.2 Register Description .......................................................................................................... 97
3.3 TLB Functions................................................................................................................... 99
Rev. 5.0, 09/03, page xix of xlvi